Не работает, ЛЕД должен светится, если '0' записываешь.
Клок процесс иррелевант пока.
Пинс правильные..


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LED is
Port ( LED : out STD_LOGIC_VECTOR (7 downto 0);
CLCK : in STD_LOGIC;
MySignal : out STD_LOGIC;
Button : in STD_LOGIC);
end LED;

architecture Behavioral of LED is

COMPONENT LED_Comp
PORT(
LED : out STD_LOGIC_VECTOR (7 downto 0);
CLCK : in STD_LOGIC;
MySignal : out STD_LOGIC;
Button : in STD_LOGIC
);
END COMPONENT;

COMPONENT clock
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;

signal clock1HzDiv : integer := 0;
signal OneHz : std_logic := '0';
signal one: std_logic := '1';
signal zero: std_logic := '0';

signal not_button: std_logic;


begin

LED(0) <= OneHz;
LED(1) <= '0';
LED(2) <= '1';
LED(3) <= '1';
LED(4) <= '1';
LED(5) <= '1';
LED(6) <= '1';
LED(7) <= '1';
MySignal <= not not_button;

CLK_stuff : process (CLCK)
begin

if rising_edge(CLCK) then
if clock1HzDiv = 25000000 then -- "After a reset, the DCM samples several thousand clock cycles to achieve lock" (http://www.xilinx.com/support/troubleshoot/clocking_debug.htm)
-- reset was de-asserted a while ago, so we should be locked by now
-- all has been clear for a while -- release the reset line
OneHz <= not OneHz;
clock1HzDiv <= 0;
end if;
end if;
end process CLK_stuff;

end Behavioral;